In this video in my CPU series, I've removed the gated clocks and in doing so, made my design easier to implement on an FPGA and also allowed for my indirect JUMP instruction to be put back in. The term "gated clock" means that the clock line of a counter, register, flip-flop, etc. is driven by a logic gate such as an AND, and not by the main clock. Some people have even forbidden the use of gated clocks.
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